Persistent demand for improved memory performance has resulted in the recent development of conventional memory systems capable of providing significantly higher data throughput. FIG. 1 illustrates such a conventional memory system in a simple block diagram. The memory system includes a memory controller (M) for writing data into and reading data from memory devices (D) via a bi-directional data bus. The memory system is configured with at least one memory device, but not more than N memory devices connected to the data bus having a predetermined characteristic impedance.
The bi-directional data bus comprises a number of signal lines, but for simplicity, only one signal line is shown in the drawings. Each signal line terminates at one end at an Input/Output (I/O) pin of the memory controller and terminates at the other end at a resistive terminator (T). The resistance of terminator (T) is closely matched to the loaded impedance of the signal line in order to minimize reflections on the signal line and absorb signals sent down the signal line towards the terminator. The other end of the terminator (T) is connected to a voltage supply (V.sub.T) which provides an AC ground and sets the DC termination voltage on the signal line.
Because the signal line is nominally pulled to the value of the termination voltage, this voltage can serve as one of the logical states for digital signals transmitted on the signal line. Switched current sources, such as open drain NMOS devices, can then be used as the signal driver circuits in either the master or memory devices. These simple signal drivers produce the logical data signals by either shutting off or sinking current as required to produce the logical states ("1" and "0"). For example, the termination voltage (V.sub.HI) can serve as the high voltage state and low logical state "0", and a low voltage state (V.sub.LO) can serve as the high logical state "1" where V.sub.LO =(V.sub.T -I.sub.O Z.sub.L) and I.sub.O is the nominal current sunk by a current source driver when it is turned "ON."
Use of this data signaling scheme has at least two benefits. First, no power is required to produce one of the logical states (V.sub.HI). Second, the current source drivers provide a high output impedance to the signal line, thereby minimizing signal energy loss as signals on the signal line propagate past the memory devices toward either end of the data bus.
When the memory controller transmits signals to one or more of the memory devices, it "sees" the full impedance, Z.sub.L, of the signal line and produces full swing signals of magnitude V.sub.SWING =(V.sub.HI -V.sub.LO) that travel down the signal line. As long as the I/O pins to the memory devices form short stubs terminated in a high impedance, little energy is lost and minimal parasitic reflections are produced as the signals propagate down the signal line and pass by the memory devices. As a rule of thumb, the stubs can be considered short if their electrical lengths are shorter than the rise and/or fall times of the signals. The signals transmitted by the memory controller propagate down the signal line, pass by all the memory devices, where they can be sensed, and eventually terminate at the terminator.
The situation is somewhat different when a memory device transmits to the memory controller. Each driver circuit in the memory device effectively "sees" two signal lines; one traveling towards the memory controller, and the other traveling towards the terminator. Thus, the net impedance seen by each driver circuit is 1/2 Z.sub.L. Assuming the driver circuits in the memory devices also sink I.sub.O current, the signals that emerge from the memory device I/O pins split at the signal line with half the signal voltage traveling towards the memory controller and half the signal voltage traveling towards the terminator. The half-V.sub.SWING signals that travel towards the terminator pass by any intervening memory devices and then simply terminate at the matched impedance of the terminator. However, the half-V.sub.SWING signals that travel towards the memory controller pass by any intervening memory devices and then encounter open circuits when they reach the memory controller I/O pins. This effectively open circuit condition causes the signals from the memory device to double in voltage at the memory controller I/O pins as the signal energy is reflected back down the signal line towards the terminator. Thus, although only half the normal signal voltage is sent by the memory devices towards the memory controller, the memory controller still receives a full voltage swing signal at its I/O pins due to the signal reflection. This is true provided the signal line terminates in a high impedance (i.e., an open circuit) at the memory controller. The other memory devices in the system will see half-normal amplitude signals pass by their I/O pins at least twice per memory device transmission. However, since the memory system is designed to transmit data from a memory device to the memory controller, and not between memory devices, this signal line condition is acceptable. Accordingly, no matter which device in the memory system is transmitting data, a full swing signal appears at the input of the intended receiving device.
The foregoing description has been made with reference to the exemplary memory system shown in FIG. 1 and in the context of individual memory devices (D) populating the data bus. However, practical memory systems often populate the data bus with memory modules, rather single memory devices. Accordingly, as shown in FIG. 2, each junction along the data bus may be occupied by a memory module comprising multiple individual memory devices.
Whether the memory system populates the data bus with memory devices or with memory modules having a plurality of memory devices, each memory device in the system is specifically assigned and subsequently identified by a device identification (ID). For example, each memory device may contain a device identification (ID) register which is assigned a unique device ID by the memory controller upon memory system initialization. During subsequent memory system operations, each memory device is activated and communicates data with the memory controller in accordance with this device ID.
As can be appreciated from the foregoing, memory system impedance is a critical system design and performance parameter. Absent a careful balance between the various memory system components noted above, the signal line impedance will depart from its desired impedance. A signal line impedance mismatch will result in unwanted signal reflections from the terminator, and in increased signal line noise associated with such undesired reflections. Increased signal line noise may, at some point, preclude discrimination of data signals at the memory devices or memory controller. This need to match signal line impedance has, to date, precluded the implementation of a truly expandable high speed memory system. That is, because the signal line impedance will necessarily change with additional loading caused by the connection of additional memory devices or memory modules to the data bus, memory system expansion required a high level of technical support and significant hardware level intervention, such as swapping out the existing terminator with a new terminator having an impedance consistent with the additional loading.
Alternatively, a physically moveable terminator can be placed between the populated portion of the data bas which has a first impedance and the unpopulated portion of the data which is terminated in a predetermined impedance and has a second impedance different from the first. This physically moveable terminator, or impedance balancing connector, is inserted in the first unoccupied "slot" on the data bus in order to maintain proper data bus impedance under variable loading conditions. U.S. Pat. No 4,595,923 more fully explains this approach.
Both of these conventional approaches to maintaining signal line impedance following the connection of additional devices require direct technician intervention. That is, a trained technician employing a special, additional part (i.e., a new terminator or an impedance balancing connector) is required to maintain signal line impedance and compensate for the additional signal line loading.
In a commercial market where customers demand the ability to customize memory system capacity and/or upgrade memory system capacity in the field, a requirement for direct technician intervention is unacceptable. Personal computer (PC) manufacturers also demand a readily definable and easily expandable memory system which may be factory configured with nearly any reasonable number of memory devices, without the requirement to customize or compensate for variable signal line impedance concerns.